AMD\'s Next Horizon Event: 7nm, Zen 2, Epyc, and Vega

AMD EPYC 'Rome': Zen 2 on 7nm, 64C/128T of CPU power

AMD's Next Horizon event this week detailed elements of its 7nm production schedule for both graphics cards and CPUs.

Two years after AMD first unveiled the brand new Zen CPU architecture that would catapult it back into the high-performance PC and server CPU markets, the company has revealed details of the next-generation Zen 2 architecture that will succeed it.

AMD CEO Lisa Su holding up pre-production Rome processor.

Rome CPUs will have up to 64 cores using a new modular "chiplet" style of architecture rather than the core complexes used by first-gen Zen CPUs. That could soon change. Based, as with its latest GPU designs, on a 7nm process node - manufactured, as if the company has a choice, at Taiwan Semiconductor (TSMC) - the Zen 2 upgrade brings with it claims of an improved execution pipeline, an improved branch predictor, better instruction prefetching, a newly optimised instruction cache, larger operation cache, enhancements to floating point performance including a doubling of width to 256-bit, and new security features - including hardware protections against the Spectre family of speculative execution vulnerabilities. In a floating-point-intensive ray tracing demonstration of a single 64-core Rome CPU prototype running alongside a dual-socket Intel Xeon Platinum 8180M server, the new AMD chip was seen to beat its competitor. A few days ago, Intel claimed that its upcoming 48-core HPC Xeon processor, known as Cascade Lake Advanced Performance (AP), would deliver 3.4 times the floating point performance on Linpack as this same EPYC chip. If you've been tracking the x86 wars for the last couple of decades, you'll know such a development is an exceedingly rare occurrence. This is a insane achievement for AMD, and really sets a new standard for compute performance. Papermaster summed it up thusly: "We're in the business of high performance".

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For now, AMD is only sharing details about Zen 2 on the server side.

According to AMD, the dedicated I/O die offers improved latency and power consumption for the new Epyc Rome processors. But because of continued delays in Intel's 10nm effort, AMD lucked out; it will be shipping some of the fastest and most power-efficient silicon in the datacenter next year. Both, regardless of model, connect to the host on a PCI Express 4.0 (PCIe 4.0) bus, while an onboard Infinity Fabric link allows for up to four GPUs to be connected together in a 'hive ring configuration' with 200GB/s of peer-to-peer bandwidth.

AMD is now sampling EPYC "Rome" chips with customers, with the chips expected to launch sometime in 2019. Not only is Rome designed for backwards compatibility with Naples platforms, but will likely be forward compatible with the impending 7nm+ third-gen Milan in 2020. A Zen 4 processor is also in the works, although no timeline was given for its debut.

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